1. Field of the Invention
The present invention relates to a resister circuit of an extended mode register set, and more particularly, to a register circuit of an extended mode register set proposed to accomplish low power consumption in a semiconductor memory device.
2. Description of Related Art
Generally, an extended mode register set (hereinafter, referred to as an xe2x80x9cEMRSxe2x80x9d) proposed to accomplish low power consumption comprises a code for controlling self refresh period (TCSR) and a code for controlling self refresh coverage (PASR), as shown in table 1.
FIG. 1 is a timing graph of EMRS command. As shown in the drawing, when CKE, /CS, /RAS, /CAS, /WE, BA1, and BA0 are in a state of H, L, L, L, L, H, and L, respectively, EMRS command is generated to set up the value of mode register.
FIG. 2 is a circuit diagram of conventional EMRS register. When EMRS command is not inputted, that is, when EMRS pin maintains low level in FIG. 2, a first inverter (IV1) is operated and a second inverter (IV2) is opened, thereby a register maintains the initial value. However, when a high level signal is applied to EMRS pin, data of pin (LA0 to LA4) are transmitted to a latch and the transmitted data are stored if a low level signal is applied to the EMRS pin. The reset of register is accomplished by a RSTM signal connected to a PUPB and data stored in reset are default values of PASR and TCSR. When a memory including EMRS is used in a chip set having no EMRS command, set up for self refresh period and coverage default value is performed totally by PUPB signal since the EMRS command is not included in a conventional memory spec.
However, considering the case that the PUPB signal is not generated even in power-up, it is required to improve the conventional extended mode register for ensuring stable reset even when the PUPB signal is not generated.
Therefore, the present invention has been made to solve the above-mentioned problems and an object of the present invention is to provide an extended mode register accomplishing stable reset.
In order to accomplish the above object, the present invention comprises: a first mode register block reset by a reset signal and outputting a predetermined level of signal in the input of extended mode register set signal; a logic block for generating an output signal by OR operation of a reset signal and a mode register set signal and masking a mode register set signal in the input of a predetermined level of signal from the first mode register block; and a second mode register block reset by output signal of the logic block.
The first and the second mode register blocks comprise a plurality of registers. The logic block comprises: a first gate performing a NAND operation to output signal of registers in the first mode register block; a second gate performing an AND operation to output signal of the first gate and a mode register set signal; and, a third gate performing an OR operation to output signal of the second gate and a reset signal.
According to the present invention, the EMRS resister can be reset by pulse type PUPB signal generated in VDD power-up and by the mode register set (hereinafter referred to as MRS). Therefore, when a memory having EMRS is used in a chip set having no EMRS, the EMRS can be stably initialized even in the case that the PUPB signal is not generated. After receiving the EMRS command, the MRS masks data of EMRS command pin to output terminal of stored register to prevent the MRS from performing reset.